1. Field of the Invention
The present invention relates to semiconductor integrated circuitry that enables a mode selection and an evaluation of the operation limit of an internal circuit only by applying a power supply voltage for test to the semiconductor integrated circuitry in test mode.
2. Description of the Prior Art
It is necessary to judge whether semiconductor integrated circuitry is defective or not prior to shipment. A high-temperature running test carried out on products continuously running at a high temperature during a fixed time interval is known as a test made to exclude early failures, for example. Such a high-temperature running test is called a burn-in test. For example, when semiconductor integrated circuitry, which is a product to be tested, is a single-chip microcomputer, the microcomputer to be tested is connected to a driver circuit by way of a data bus signal line, an address signal line and a control signal line, and the burn-in test is carried out in such a manner that a power supply voltage for test of about 7.0 Volts which is higher than a normal power supply voltage (4.5 to 5.5 Volts) applied to the microcomputer under normal operating conditions is applied to the microcomputer at a high temperature which exceeds 100xc2x0 C. and the microcomputer is made to operate continuously during a fixed time interval.
FIG. 12 is a schematic circuit diagram showing the structure of an example of prior art semiconductor integrated circuitry. In the figure, reference numeral 1 denotes the semiconductor integrated circuitry which is a single-chip microcomputer, numeral 2 denotes an internal circuit which is an integrated circuit including a logic circuit etc., numeral 3 denotes an I/O circuit including an input/output terminal 3a and an output buffer 3 b for connecting the internal circuit 2 to an external circuit (not shown in the figure), numeral 4 denotes a voltage drop control (VDC) circuit that consists of a reference voltage generation circuit 4a and a voltage drop circuit 4b, numeral 5 denotes a power supply switch circuit for selecting either an external power supply or a power supply for test and for connecting the selected power supply to the internal circuit 2, numeral 6 denotes an external power supply terminal via which the external power supply is supplied to the semiconductor integrated circuitry 1, numeral 7 denotes a power supply terminal for test via which the power supply for test is supplied to the semiconductor integrated circuitry 1 in the test mode, and numeral 8 denotes a power supply control terminal for controlling the power supply switch circuit 5 so that the power supply switch circuit 5 switches between the two selection modes.
In operation, when the semiconductor integrated circuitry 1 is actually used as a product, that is, when the semiconductor integrated circuitry 1 operates in the normal operation mode, the semiconductor integrated circuitry 1 is used in a state in which the power supply for test is not connected to the power supply terminal 7 for test while the external power supply (not shown in the figure) is connected to the external power supply terminal 6. In this case, the external power supply voltage Vc is supplied to the I/O circuit 3 and the voltage drop control circuit 4. The reference voltage generation circuit 4a included in the voltage drop control circuit 4 consists of a plurality of diodes (not shown in the figure) in series, for example, and the sum of the forward voltage drops by the individual diodes is furnished as a reference voltage Vr to the voltage drop circuit 4b. If the external power supply voltage Vc is 5 Volts, this reference voltages Vr is set to be about 4 Volts which is slightly lower than the external power supply voltage and is then supplied as a target dropped voltage to the voltage drop circuit 4b which is the next stage of the voltage drop control circuit 4. The voltage drop circuit 4b controls the external power supply voltage Vc so as to decrease the external power supply voltage Vc to the reference voltage Vr, and supplies the decreased external power supply voltage to the power supply switch circuit 5. In the normal operation mode, the power supply switch circuit 5 is in the state of connecting the voltage drop circuit 4b to the internal circuit 2, and, therefore, the output voltage of the voltage drop circuit 4b is supplied to the internal circuit 2 by way of the power supply switch circuit 5. In this case, although an influence of any change in the external power supply voltage Vc is exerted on the I/O circuit 3, the internal circuit 2 can be made to operate with stability without independently of any change in the external power supply voltage Vc because the voltage drop circuit 4b controls the external power supply voltage Vc so as to decrease the external power supply voltage Vc to the reference voltage Vr.
On the other hand, in the test mode for an evaluation of the operation limit of the internal circuit 2, the power supply (not shown in the figure) for test is connected to the power supply terminal 7 for test, and a switch instruction is furnished by way of the power supply control terminal 8 to the power supply switch circuit 5. As a result, since the internal circuit 2 is connected to the power supply for test by way of the power supply terminal 7 for test and the I/O circuit 3 is connected to the external power supply by way of the external power supply terminal 6, two kinds of tests: an internal circuit test and an I/O circuit test can be carried out. When carrying out the internal circuit test, only the power supply voltage Vd for test to be applied to the internal circuit 2 is changed without changing the external power supply voltage Vc to be applied to the I/O circuit 3. As a result, whether the internal circuit 2 can handle any change in the power supply voltage for test while having a margin up to which extent for the voltage change is tested, and an evaluation of the operation limit of the internal circuit 2 can thus be made. On the other hand, when carrying out the I/O circuit test, only the external power supply voltage Vc to be applied to the I/O circuit 3 is changed without changing the power supply voltage Vd for test to be applied to the internal circuit 2. As a result, whether the I/O circuit 3 can handle any change in the external power supply voltage while having a margin up to which extent for the voltage change is tested, and an evaluation of the operation limit of the I/O circuit 3 can thus be made.
A problem with the prior art semiconductor integrated circuitry 1 constructed as above is that the power supply switch circuit 5 and the two terminals: the power supply terminal 7 for test and the power supply control terminal 8 are indispensable to make an evaluation of the operation limit of the internal circuit, and the circuit structure is therefore complicated. Another problem with the prior art semiconductor integrated circuitry 1 is that since a connecting line having a capacity of large current is needed as a feedline for connecting the power supply terminal 7 for test to the power supply switch circuit 5, the large-current connecting line can interfere with an improvement of the packaging density on a circuit board on which the internal circuit 2 is mounted.
The present invention is proposed to solve the above-mentioned problems, and it is therefore an object of the present invention to provide semiconductor integrated circuitry that enables a mode selection and an evaluation of the operation limit of an internal circuit only by applying a power supply voltage for test to the semiconductor integrated circuitry in the test mode.
In accordance with the present invention, there is provided semiconductor integrated circuitry comprising: an internal circuit that is an semiconductor integrated circuit; an I/O circuit for activating an input/output of the internal circuit in response to an external power supply voltage applied thereto; a reference voltage generation circuit for decreasing the external power supply voltage so as to generate a constant reference voltage; a voltage drop circuit for controlling the external power supply voltage so as to decrease it such that it is equal to an input voltage applied thereto, and for supplying the decreased external power supply voltage to the internal circuit; and a mode determination control circuit to which a power supply voltage for test is supplied from a power supply for test that is connected to a power supply terminal for test in test mode, for comparing the power supply voltage for test with a threshold voltage so as to determine whether the semiconductor integrated circuitry is placed in either normal operation mode or the test mode, and for supplying either the reference voltage or the power supply voltage for test to the voltage drop circuit as the input voltage according to the mode determination result.
In accordance with a preferred embodiment of the present invention, the mode determination control circuit includes a mode determination unit having a pair of inverters in series having an input terminal for receiving the power supply voltage for test, and a switching unit having a pair of transmission gates, for selectively supplying either the reference voltage or the power supply voltage for test to the voltage drop circuit, the pair of transmission gates having output terminals connected in common to the voltage drop circuit, one of the transmission gates having an input terminal connected to the power supply terminal for test and the other transmission gate having an input terminal connected to the reference voltage generation circuit, and only one of the pair of transmission gates being switched to its conducting state in response to two outputs of the inverters included in the inverter pair. Preferably, a first-stage one of the pair of inverters inverts its output voltage based on a logical threshold voltage that is equal to or less than one-half of the external power supply voltage.
In accordance with another preferred embodiment of the present invention, the mode determination control circuit includes a mode determination unit having three inverters in series having an input terminal for receiving the power supply voltage for test, and a switching unit having a pair of transmission gates, for selectively supplying either the reference voltage or the power supply voltage for test to the voltage drop circuit, the pair of transmission gates having output terminals connected in common to the voltage drop circuit, one of the transmission gates having an input terminal connected to the power supply terminal for test and the other transmission gate having an input terminal connected to the reference voltage generation circuit, and only one of the pair of transmission gates being switched to its conducting state in response to two outputs of two of the three inverters in series other than a first-stage one of them. Preferably, a first-stage one of the three inverters in series inverts its output voltage based on a logical threshold voltage that is equal to or greater than one-half of the external power supply voltage.
In accordance with another preferred embodiment of the present invention, the mode determination control circuit includes a resistor located on a line for connecting the reference voltage generation circuit to the voltage drop circuit, and a power supply voltage supply line for test for supplying the power supply voltage for test to a node located between the resistor and the voltage drop circuit.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.